An Overview of VLSI Memory Yield Management by Injection of Fault Tolerance

Abstract

Presents an overview of memory chip yield enhancement techniques by injection of fault tolerance. As memory chips are more prone to defects, the yield of good chips from a silicon wafer governs their production cost. As shown, most fault tolerance techniques assume a relatively large area overhead which results in additional costs in terms of the silicon used as well as the lower number of chips/wafers produced. Proper management of fault tolerance, as by the word redundancy approach, adds an almost negligible area overhead to the chip and leads to considerably higher yields.

Citation

Mehdi, K.A. and Kontoleon, J.M. (1994), "An Overview of VLSI Memory Yield Management by Injection of Fault Tolerance", International Journal of Quality & Reliability Management, Vol. 11 No. 3, pp. 43-54. https://doi.org/10.1108/02656719410056477