Inner‐layer copper reliability of electroless copper processes

Abstract

Purpose

The purpose of this paper is to present an overview of the alternative testing approaches that may be used to assess interconnect quality and their application to laminate material and plated‐through‐hole (PTH) process control.

Design/methodology/approach

The paper introduces the importance of inner‐layer copper reliability and how to evaluate it. It reviews and discusses the effects of all factors involved, including laminate material, panel design, and chemical controls, on interconnect defects (ICDs).

Findings

The best possible reliability can only be achieved by implementation of process controls ranging from incoming laminate material inspection to drilling parameters and finally chemical controls within the electroless copper process.

Research limitations/implications

This paper focuses on through‐hole multilayer reliability. Although blind via reliability shares some aspects with through‐hole reliability, there are other factors that only apply to blind vias. This area will be the subject of a future publication.

Originality/value

The paper provides an overall review, integrating information on the whole electroless copper process, starting from ICD testing methods, and including the effects of laminate material, desmear, and PTH control. It provides a reference for readers involved in trouble shooting or process improvement.

Citation

Li, C.P.L., Ciccolo, P. and Yee, D.K.W. (2010), "Inner‐layer copper reliability of electroless copper processes", Circuit World, Vol. 36 No. 1, pp. 31-37. https://doi.org/10.1108/03056121011015077