Abstract
Purpose
Porous silicon (Si) was fabricated by using three different wet etching methods, namely, direct current photo-assisted electrochemical (DCPEC), alternating CPEC (ACPEC) and two-step ACPEC etching. This study aims to investigate the structural properties of porous structures formed by using these etching methods and to identify which etching method works best.
Design/methodology/approach
Si n(100) was used to fabricate porous Si using three different etching methods (DCPEC, ACPEC and two-step ACPEC). All the samples were etched with the same current density and etching duration. The samples were etched by using hydrofluoric acid-based electrolytes under the illumination of an incandescent lamp.
Findings
Field emission scanning electron microscopy (FESEM) images showed that porous Si etched using the two-step ACPEC method has a higher porosity and density than porous Si etched using DCPEC and ACPEC. The atomic force microscopy results supported the FESEM results showing that porous Si etched using the two-step ACPEC method has the highest surface roughness relative to the samples produced using the other two methods. High resolution X-ray diffraction revealed that porous Si produced through two-step ACPEC has the highest peak intensity out of the three porous Si samples suggesting an improvement in pore uniformity with a better crystalline quality.
Originality/value
Two-step ACPEC method is a fairly new etching method and many of its fundamental properties are yet to be established. This work presents a comparison of the effect of these three different etching methods on the structural properties of Si. The results obtained indicated that the two-step ACPEC method produced an etched sample with a higher porosity, pore density, surface roughness, improvement in uniformity of pores and better crystalline quality than the other etching methods.
Keywords
Citation
Zulkifli, F., Radzali, R., Abd Rahim, A.F., Mahmood, A., Mohd Razali, N.S. and Abu Bakar, A. (2022), "Influence of different etching methods on the structural properties of porous silicon", Microelectronics International, Vol. 39 No. 3, pp. 101-109. https://doi.org/10.1108/MI-01-2022-0009
Publisher
:Emerald Publishing Limited
Copyright © 2020, Emerald Publishing Limited
1. Introduction
The discovery of porous silicon (Si) at Bell Laboratories by A. Uhlir Jr. in the 1950s, in which it was physically formed through the anodic dissolution of single crystalline Si in hydrofluoric acid (HF) solutions (Uhlir, 1956) and visible photoluminescence (PL) from porous Si at room temperature, has since garnered much research interest (Canham, 1990). Nowadays, due to its unique features such as high surface area, wide band gap and decrease of reflecting losses, porous Si is used in many electronic and optoelectronic devices (Rahim et al., 2020; Omar and Salman, 2017) such as solar cells (Omar and Salman, 2017) and gas sensors (Ramizy et al., 2011).
According to the literature, few methods can be used to fabricate porous samples and can be classified as dry or wet etching techniques. Dry etching techniques such as inductively coupled plasma reactive ion etching are very costly compared to wet etching methods and can cause surface damage to the thin film during the etching process which will degrade the properties of the porous structure (Choi et al., 2000, 2002). On the contrary, wet etching has shown more advantages as it requires simple equipment and low processing temperatures, producing little structural damage, alongside being versatile and more cost effective than dry etching methods. Some of the wet etching methods that are generally used to fabricate porous Si include electroless etching (Vajpeyi et al., 2005) and direct current photo-assisted electrochemical (DCPEC) etching (Yang et al., 2021). Electroless etching is an etching method where the nano-structures are fabricated unselectively on the whole Si and catalysed by metals without an external bias (Brahiti et al., 2012). This technique requires strong oxidising species which should be able to inject holes into the valence band of the semiconductor. However, this technique often produces non-uniform pores (Yam and Hassan, 2009). On the other hand, the photo-assisted electrochemical etching method using a DC or DCPEC as the power supply has gained more interest from many researchers (Atta et al., 2021; Yang et al., 2021) than the electroless etching in fabricating porous structures due to the controllability over the etching process by varying the etching parameters. However, the DCPEC method has a disadvantage in which this etching method produces hydrogen bubbles that can hinder the etching process and result in non-uniform pore formation, lower etching rates and a low density of pores (Naderi and Hashim, 2012a, 2012b). Therefore, to improve the surface morphology, few works have reported on the electrochemical etching method using an alternating current (AC) instead of DC as the power supply (Abd et al., 2013). Through the alternating CPEC (ACPEC) etching technique, anodisation process for the pore formation occurs at the anodic half cycle and the cathodic half cycle will contribute to reduce the formation of hydrogen bubbles which solve the problem deriving from the DCPEC method (Mahmood et al., 2013). A research work done by Rahim et al. (Rahim et al., 2020) reported a high porosity distribution of porous Si obtained after 30 min of etching using the ACPEC method. However, the pores produced were shallow.
Therefore, to further enhance the pore density, depth, and uniformity of porous Si structures, a new etching technique, which is a two-step alternating CPEC (ACPEC) method has recently been carried out by our research group to fabricate porous Si (Radzali et al., 2017, 2021). In this new method, the sample was etched initially for a few minutes and followed by ACPEC etching. Since the study of the two-step ACPEC is still in the early stage, many of its fundamental properties are not yet well established. Therefore, it is of interest in this work to investigate the effect of different etching methods towards the structural properties of porous Si. To the best of our knowledge, the comparison on the effect of these three different etching methods on the structural properties of porous Si has not yet been reported. In this work, the structural properties of the porous Si were investigated via field emission scanning electron microscopy (FESEM), atomic force microscopy (AFM), and high resolution X-ray diffraction (HR-XRD).
2. Experimental procedures
N-type Si (100) was used in this work to fabricate porous Si structures. The Si n(100) wafers were cut into small pieces with dimensions of 1 cm × 1cm. Before starting the etching process, the samples were cleaned using the Radio Corporation of America (RCA) cleaning method to remove any impurities which could affect the etching process. Figure 1 shows the experimental setup for the etching process.
A Teflon cell with an O-ring and metal plate was used to hold the sample and electrolyte during the etching process. The Si sample was placed between the O-ring and the metal plate. The front side of the sample was placed in contact with the electrolyte, which was a mixture of HF and ethanol with volume ratio of 1:4. This electrolyte has commonly been used to fabricate porous Si by other research groups (Rahim et al., 2020, 2016; Wahab et al., 2020; Radzali et al., 2017, 2021). The platinum wire acted as a cathode during the etching process while the metal plate acted as an anode. The ammeter was used to monitor the current supply and the sample was illuminated under an incandescent lamp throughout the etching process.
In this work, different types of etching method were employed to fabricate the porous Si which were DCPEC, ACPEC, and the two-step ACPEC method. The same experimental setup was applied for DCPEC, ACPEC and the two-step ACPEC method as shown in Figure 1. For the DCPEC method, a DC power supply was used to supply DC during the etching process. Meanwhile, for the ACPEC method, an AC power supply was used to supply AC. The two-step ACPEC differed slightly from the other two methods. As the name implies, there were two steps to the etching process. In the first step, the sample was left immersed in the electrolyte for a few minutes to form a high density of etch pits (Radzali et al., 2021). Subsequently, in the second step, the sample was etched using the ACPEC method with the same electrolyte. The current density for all etching methods was set at 20 mA/cm2 and the etching duration was 30 min. The current density and etching duration were those that are generally applied in fabricating porous Si structures (Rahim et al., 2020). Then, the porous sample was rinsed with deionised water after the etching process and left to dry under ambient air.
All of the samples were characterised for their structural properties using FESEM (Model: Jeol JSM 7401 F), AFM (Model: Dimension EDGE, BRUKER) and HR-XRD (Model: PANalytical X’pert Pro MRD).
3. Results and discussion
3.1 Field emission scanning electron microscopy
Several research groups have proposed mechanisms for the formation of porous Si structures (Föll et al., 2010; Lehmann, 1993). The mechanism of pore formation in this work is explained as follows. Pore formation on the Si surface occurred through the dissolution of Si in HF-based electrolytes. The HF-based electrolyte has properties that allow the dissolution of the passivated Si surface. During the etching process, holes are required for the dissolution of Si atoms. These holes play a significant role in converting the surface atom to a higher oxidation state. However, the number of holes thermally generated at room temperature is very small and on top of that, holes are the minority carriers for n-type Si. Therefore, in order to increase the number of holes, the Si sample is illuminated with light to generate holes optically. The generated holes are attracted to the Si surface as the Si sample is positively biased, whereas the platinum wire immersed in the HF-based electrolyte is negatively biased. When holes are injected into the Si surface, it prompts the oxidation of a nearby Si atom at the surface which is then attacked by bifluoride ions and dissolved by a divalent charge transfer. Thus, the Si atom removal is accelerated by the injected holes. For each Si atom dissolved, two hydrogen atoms evolve during the formation of the porous structure. The reaction during the pore formation proposed by Beale et al. (1985) is as follows:
The etch rate using electrolytes without an external bias to etch single crystal Si is relatively low. Therefore, during the etching process, the etching rate can be increased by applying an external electric current between the HF-based electrolyte and the Si sample (Lehmann, 2002). In order to prevent porous structures from turning inhomogeneous and avoid the peeling of some part of the substrate, a certain amount of current density at a given HF concentration must not be exceeded to form a porous layer (Bisi et al., 2000). The DCPEC method has a low etching rate due to the hydrogen bubbles that form during the etching process (Naderi and Hashim, 2012a, 2012b). Meanwhile, the ACPEC method could reduce the hydrogen bubbles which allow the HF-based electrolyte to react with the Si surface, increasing the etching rate and porosity of porous Si structures (Mahmood et al., 2013). On the other hand, the two-step ACPEC method produces a high density of etch pits during the first step and applies the ACPEC method in the second step (Radzali et al., 2021). By combining both steps in the two-step ACPEC method, the etching rate was increased and the porous Si structure produced a high porosity with improvement in terms of pore uniformity. Interestingly, applying different etching methods resulted in different porous Si structures as observed in the FESEM images.
Figure 2 shows the FESEM images of the as-grown Si sample and porous Si samples etched using the DCPEC, ACPEC and two-step ACPEC method. The ImageJ software was used to examine the average pore length, width, diameter, and estimated porosity for each sample as summarised in Table 1. The inset image of Figure 2 shows the measurement of pore length, width, and diameter. The pore length and width were measured from the crisscross pores while the pore diameter was measured from the circular and square-shaped pores. On the other hand, the estimated porosity percentage was measured using the ImageJ software by counting the number of pixels of the pores and the whole surface area of the FESEM image. Following this, the porosity was determined as the ratio of the total pore area over the entire Si sample surface (Astuti et al., 2018; Sulka, 2008). Therefore, the total pore area and porosity of the porous structure could be quantitatively estimated with the combination of FESEM images and the use of the ImageJ software. The formation of pores was observed on the Si surface after the etching process.
Figure 2(a) shows the as grown sample which represents the sample before it underwent the etching process. The surface of this sample was very smooth and flat without any pores or ridges. Therefore, porosity value was not determined for this sample.
Figure 2(b) shows the porous Si sample etched using the DCPEC method showing that the majority of pores had a crisscross shape and, few small and shallow circular pores occurred between the crisscross-shaped pores. From the image, it can be seen that the porous structure was not uniformly formed. The average pore lengths and widths of the crisscross pores were measured to be ∼3.596 µm and ∼0.337 µm, respectively. In addition, the pore diameter of the small circular pores was ∼0.265 µm and the estimated porosity was calculated to be 10.809%. The porous Si sample etched using the DCPEC method had the lowest estimated porosity compared to the porous Si samples etched using the ACPEC and two-step ACPEC methods due to the hydrogen bubbles formed during the etching process which hindered the formation of pores and caused the DCPEC method to have a low etching rate (Naderi and Hashim, 2012a, 2012b).
Figure 2(c) shows the porous Si structure for samples etched using the ACPEC method. Although the pore shape formed using the ACPEC method was similar to the sample etched by DCPEC, which showed crisscross-shaped and some circular pores, the sample etched with the ACPEC method exhibited a higher pore density than the sample etched with the DCPEC method. Furthermore, the circular pores on this sample were deeper (visible as darker areas) than in the sample etched by DCPEC. The average pore length and pore width of the crisscross-shaped pore for this sample were ∼2.243 µm and ∼0.413 µm, respectively. Although the average pore length was lower than in the porous Si sample etched with the DCPEC method, the porous Si sample etched with the ACPEC method had a higher average pore width than the DCPEC sample. Moreover, the average pore diameter for the porous Si sample etched using ACPEC was higher than the porous Si sample etched using the DCPEC method which was measured to be ∼0.397 µm. Besides, the estimated porosity for the sample etched by ACPEC was 16.218%, which was higher than in the sample etched by DCPEC. The sample etched by ACPEC had a higher porosity than the sample etched by DCPEC because the ACPEC method helped in reducing the hydrogen bubbles, which allowed the electrolyte to react with the Si surface, resulting in higher etching rates and porosity (Radzali et al., 2021).
Figure 2(d) shows the image of the porous Si structure for the sample etched using the two-step ACPEC method and it could be seen that this sample was more densely packed with pores and showed improvements in terms of pore uniformity compared to the porous Si samples etched with the DCPEC and ACPEC method. Figure 2 shows that there were crisscross-shaped pores formed along with square-shaped pores. In addition, some of the square-shaped pores were formed at the intersection of the crisscross-shaped pores. The average pore length of the crisscross-shaped pore was measured to be ∼2.818 µm, which was higher than in the ACPEC sample but lower than in the DCPEC one. Meanwhile, the average pore width of the crisscross-shaped pore was greater than in both porous Si samples etched using DCPEC and ACPEC, which was ∼0.449 µm. On the other hand, the average pore diameter measured for the porous Si sample etched using the two-step ACPEC method was ∼0.616 µm which was higher than in the samples etched with the other two methods. In addition, amongst the porous Si samples, the sample etched with two-step ACPEC exhibited the highest estimated porosity (24.434%). The high porosity of the sample etched with the two-step ACPEC method could be due to the etching process of this method in which, the first step of this method allowed the formation of a high density of etch pits as mentioned previously, which helped to increase the formation of pores on the Si sample (Radzali et al., 2017, 2021). During this step, with the lack of current supply, the chemical etching had an effect whereby the crystalline Si surface was exposed to the oxidant and etchant chemicals in the electrolyte solution. Thus, the oxidation and reduction sites occurred randomly on the Si surface. The localisation of primary pores occurs as random points on crystalline Si (Megouda et al., 2009; Naderi and Hashim, 2012a, 2012b) since the whole Si surface has equal etching parameters which leads to homogenous pore formation. Hence, this etching process fabricated shallow but uniform pores on the Si sample which could be used as a template to produce deep and homogenous pores in the second step. The ACPEC technique was applied during the second step. In this etching technique, an AC current was supplied. As mentioned previously, holes play an important role during the etching process. The supply of holes accessible at the Si surface to partake in the oxidation reaction was greatly enhanced due to the absorption of the incident radiation which resulted in significantly enhanced etching rates (Mahmood et al., 2013). During the etching process, the holes that were required for the etching process were supplied during the positive half cycle of the AC current (Mahmood et al., 2013). Additionally, the hydrogen bubbles were reduced during the negative half cycle which allowed the HF to react directly with the Si surface. Thus, increasing the etching rate of this method also improved the pore uniformity, porosity and density of the porous Si sample etched using the two-step ACPEC method as shown in Figure 2(d). Overall, the results thus far show that different etching methods result in different types of porous structures. Moreover, the higher porosity exhibited in porous samples etched using the two-step ACPEC method relative to the as grown and other etching methods shows that the porous Si has the potential to be used in sensing applications such as gas and humidity sensors.
3.2 Atomic force microscopy
Figure 3 shows the AFM measurements for the as-grown Si sample and porous Si samples etched using the DCPEC, ACPEC and two-step ACPEC methods. Table 2 records the data obtained from the AFM measurements. The NanoScope analysis software was used to measure the average surface roughness in root mean square (RMS). The average pore depth was measured and estimated using the line scan function in the NanoScope analysis software which is a non-destructive method to estimate a pore depth. The pore depth was determined from the cross-section line scan and measured by the vertical distance of two cursors from the sample surface until the depth of the pore as shown in Figure 3. Several cross-section line scans and the vertical distance were measured and the obtained value of the pore depth was averaged. A similar method has been used by other researchers to estimate the average pore depth of porous samples (Hou et al., 2001; Sohimee et al., 2018; Almanza-Workman et al., 2003; Razali et al., 2019; Radzali et al., 2013, 2014; Rahim et al., 2020).
According to the AFM measurements, the as-grown Si sample displayed a low surface roughness (0.296 nm) evidencing the smooth surface of the sample. As there were no pores on the as grown sample, the average pore depth value was not measured for this sample. On the other hand, the etching process changed the surface morphology of the Si thin film in which all the etched samples showed a significantly higher surface roughness than the as grown sample because the surface of as-grown Si sample had been altered during the etching process (Sohimee et al., 2020).
As shown in Table 2, the sample etched using the DCPEC method showed the highest average pore depth of ∼265.246 nm, followed by the samples etched using the two-step ACPEC and ACPEC methods which had average pore depths of ∼260.832 nm and ∼152.234 nm, respectively. Although the results showed that the DCPEC method produced deeper pores than the other two etching methods, the porous Si sample etched with the DCPEC method had the lowest value of surface roughness with an RMS value of 177.0 nm. The low surface roughness of the porous Si sample etched with the DCPEC method was associated with the formation of hydrogen bubbles during the DCPEC etching process which hindered the etching process and reduced the etching rate (Abd et al., 2013), resulting in a low pore density as shown in the FESEM image in Figure 2(b).
On the other hand, the porous Si sample etched with ACPEC method formed shallow pores with an average measured pore depth of ∼152.234 nm. Similar results had been observed in work by Rahim et al. (2020) which showed that shallow pores were produced using this method; ∼8.934 nm for porous Si n(100) and ∼59.894 nm for porous Si n(111). However, the porous Si sample etched with the ACPEC method exhibited more pore formation and had a slightly higher surface roughness with an RMS value of 178.0 nm relative to the sample treated with the DCPEC method. The ACPEC method improved the pore density and surface roughness of the porous Si, as this method was able to reduce the formation of hydrogen bubbles during the etching process (Naderi et al., 2012; Radzali et al., 2021), resulting in higher etching rates.
Furthermore, the porous Si sample etched using the two-step ACPEC method exhibited deeper pores than the one etched with ACPEC, with a value of ∼260.832 nm. It is worth noting that, amongst the etched samples, the two-step ACPEC method produced a porous Si structure with the highest value of surface roughness (RMS of 215.0 nm). Moreover, the results obtained in our work using the two-step ACPEC method showed higher RMS values than the results obtained by Sohimee et al. (2018) on porous Si etched using the ACPEC method. The high surface roughness of the porous Si sample etched with the two-step ACPEC method is consistent with the FESEM image shown in Figure 2(d) where the porous Si sample shows pore uniformity and a high density of pores, resulting in a high surface roughness in this porous Si sample. According to these results, the two-step ACPEC could increase both the surface roughness and pore depth of porous Si samples. The reason for the increment in the surface roughness and the pore depth of porous Si could be associated with the two-step ACPEC etching method or mechanism that was explained earlier. In the two-step ACPEC method the chemical etching in the first step helped to form a high density of etch pits in which, as mentioned previously, shallow but uniform pores were produced on the Si sample which become a template for the second step. Meanwhile in the second step, the Si sample was etched using ACPEC, potentially helping to reduce the formation of hydrogen bubbles during the etching process and allowing the electrolyte to react with the Si surface to form deeper pores which resulted in high etching rates (Rahim et al., 2016; Naderi, 2013; Radzali et al., 2017, 2021). Therefore, when the AC current was applied, deeper pores were produced following the pore template. The high surface roughness shown in the two-step ACPEC porous Si sample indicates that such a structure shows good potential for optical and sensor applications such as in gas and humidity sensors.
3.3 High resolution X-ray diffraction
Figure 4 shows the 2θ-scan of HR-XRD patterns for the as grown and porous Si samples etched using the DCPEC, ACPEC and two-step ACPEC methods. The inset image shows a close-up of the porous Si samples’ peak intensity. The obtained results were used to evaluate the crystalline properties of the samples.
According to Figure 4, the peak position for all the samples occurred at about 69° represented by a (400) reflection of the cubic phase. There were no peak shifts for the porous Si samples relative to the as-grown Si sample indicating that no stress was experienced during the etching process (Rahim et al., 2016). Similar results have been observed by Rahim et al. (2016). On the other hand, the peak intensities for all the porous Si samples were noted to be lower than the as-grown Si sample’s as the etching process influenced the formation of pores (Sohimee et al., 2020) due to the Si thin film diminishing during the etching process. Similar results could be observed where the peak intensities of porous Si samples were lower than those of the as grown sample (Rahim et al., 2020; Sohimee et al., 2020). It was observed that the porous Si sample etched with the ACPEC method had the lowest peak intensity out of all etched samples. In addition, the sample etched with the DCPEC method showed a higher peak intensity than the ACPEC sample, while the sample etched with the two-step ACPEC method, albeit displaying a slightly higher peak intensity than the porous Si sample etched using the DCPEC method, exhibited the highest peak intensity out of the samples treated with the three etching methods. The porous Si sample etched using the two-step ACPEC method had the highest peak intensity suggesting that the uniform formation of pores resulted in a better crystalline structure than the other porous Si samples (Rahim et al., 2016). Therefore, the formation of pores did not affect the peak position of the porous samples; nevertheless, different etching methods affected the peak intensities of porous samples. Table 3 shows the summary of the data obtained from the HR-XRD measurements.
The crystallite size of the samples can be calculated with the Debye-Scherrer equation (2) using the results obtained from the HR-XRD measurements as shown below:
Where D is the average crystallite size, λ is the X-ray wavelength (0.15406 nm), β is the full-width-half-maximum (FWHM) in radians and the θ is the diffraction angle in radians. According to Table 3, the porous Si samples etched using the DCPEC, ACPEC and two-step ACPEC methods exhibited higher values of crystallite size of 10.83 nm, 6.71 nm, and 5.48 nm, respectively, compared to the as-grown Si sample. This result could be attributed to the broadening of the XRD peak. The broadening of the peak not only contributed to the reduced crystallite size but also to the effect of size confinement (Al-Jumaili et al., 2016). Therefore, different etching methods resulted in different morphologies and crystallinities.
4. Conclusions
Porous Si samples were successfully fabricated using three etching methods which were DCPEC, ACPEC and two-step ACPEC. The FESEM results showed that sample etched using the two-step ACPEC method had the highest pore density and porosity, and improvement in the uniformity of pores relative to the samples treated with the other two etching methods. The AFM measurements also supported FESEM results as the two-step ACPEC sample exhibited a higher surface roughness value in RMS than the samples etched using the other two methods. The two-step ACPEC method improved the disadvantages of the other two etching methods by producing a higher pore density, porosity, surface roughness value in RMS, and an improvement in terms of pore uniformity. The results from HR-XRD measurements indicated that there was an improvement in the crystalline quality of the porous Si sample etched by two-step ACPEC. In conclusion, of all considered etching techniques, the two-step ACPEC method was most helpful in improving the structural properties of the porous Si samples. Therefore, the results obtained in this work show the potential of porous Si for sensing devices such as gas and humidity sensors. In future work, other etching conditions could be varied to improve the properties of porous Si structures.
Figures
Summary of pore size and estimated porosity for as grown Si and the porous Si samples etched using different etching methods
| Sample | Average pore length (µm) | Average pore width (µm) | Average pore diameter (µm) | Estimated Porosity (%) |
|---|---|---|---|---|
| As grown | – | – | – | – |
| DCPEC | 3.596 | 0.337 | 0.265 | 10.809 |
| ACPEC | 2.243 | 0.413 | 0.397 | 16.218 |
| Two-Step ACPEC | 2.818 | 0.449 | 0.616 | 24.434 |
Summary of atomic force microscopy (AFM) measurements of as grown Si and porous Si samples etched using different etching methods
| Sample | Average pore depth (nm) |
Surface roughness in RMS (nm) |
|---|---|---|
| As grown | – | 0.296 |
| DCPEC | 265.246 | 177.0 |
| ACPEC | 152.234 | 178.0 |
| Two-step ACPEC | 260.832 | 215.0 |
Summary of the peak position, FWHM value and crystallite size of the as grown and porous Si samples etched using the DCPEC, ACPEC and two-step ACPEC methods
| Sample | 2θ (°) | FWHM (°) | Crystallite size (nm) |
|---|---|---|---|
| As grown | 69.125 | 0.11 | 91.58 |
| DCPEC | 69.125 | 0.93 | 10.83 |
| ACPEC | 68.925 | 1.50 | 6.71 |
| Two-step ACPEC | 69.175 | 1.84 | 5.48 |
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Further reading
Yeon, H.J., Akbar, Z.A., Lee, J.S., Hahn, J.R., Joh, H.I., Jang, S.Y. and Lee, S. (2016), “Fabrication of porous carbon films and their applications for electrocatalytic electrodes”, Science of Advanced Materials, Vol. 8 No. 1, pp. 57-63.
Acknowledgements
This research was supported by the Ministry of Higher Education (MOHE) through the Fundamental Research Grant Scheme 2021 (Grant No. FRGS/1/2021/STG07/UITM/02/8). The authors would also like to acknowledge the support from Universiti Teknologi MARA, Cawangan Pulau Pinang and INOR lab staff of Universiti Sains Malaysia (USM) in completing this research.
Corrigendum: It has come to the attention of the publisher that the article Zulkifli, F., Radzali, R., Abd Rahim, A.F., Mahmood, A., Mohd Razali, N.S. and Abu Bakar, A. (2022), “Influence of different etching methods on the structural properties of porous silicon”, Microelectronics International, Vol. 39 No. 3, pp. 101-109. https://doi.org/10.1108/MI-01-2022-0009 did not include the correct wording in the acknowledgements section. This error was introduced during the submission process. “The authors would like to acknowledge the support from Universiti Teknologi MARA, Cawangan Pulau Pinang and INOR lab staff of Universiti Sains Malaysia (USM) in completing this research.” This research was supported by the Ministry of Higher Education Malaysia (MOHE) through Fundamental Research Grant Scheme (Grant No. FRGS/1/2021/STG07/UITM/02/8) has been changed to This research was supported by the Ministry of Higher Education (MOHE) through the Fundamental Research Grant Scheme 2021 (Grant No. FRGS/1/2021/STG07/UITM/02/8). “The authors would also like to acknowledge the support from Universiti Teknologi MARA, Cawangan Pulau Pinang and INOR lab staff of Universiti Sains Malaysia (USM) in completing this research”. The authors sincerely apologise for this error and for any misunderstanding.
Corresponding author
About the authors
Fatimah Zulkifli obtained her B.Eng Hons in Electronics Engineering program under Faculty of Electrical Engineering, UiTM, Shah Alam. Currently, she is undertaking MSc. study at UiTM Pulau Pinang. Her research interests are in the fabrication and characterization of porous structures for application in semiconductor devices.
Rosfariza Radzali obtained her B.Eng. in Electronics and System from Takushoku University, Japan and MSc in Microelectronics from Unversiti Kebangsaan Malaysia. She obtained PhD from Universiti Sains Malaysia in Semiconductor Fabrication. Her research interests are in nanostructure fabrication and characterization of III-Nitrides (GaN, InGaN, InAlGaN) and silicon semiconductors for application in sensing devices such as gas sensors, photodetectors. On top of that, she is also interested in modelling and simulation of semiconductor devices using Silvaco TCAD Tools. She is currently a Senior Lecturer at the Faculty of Electrical Engineering, Universiti Teknologi MARA, Malaysia.
Alhan Farhanah Abd Rahim obtained B.Eng. Hons in Electronics Engineering from the University of Southampton in 1998, MSc and PhD in Solid State Physics from Universiti Sains Malaysia in 2003 and 2014, respectively. She is currently a senior lecturer at the Faculty of Electrical Engineering, Universiti Teknologi MARA, Malaysia. Her research interests are in synthesizing and fabricating advanced semiconductor materials (Si, Ge, GaN) and devices utilizing low-cost techniques. She is the author and co-author of over 40 scientific publications in this field.
Ainorkhilah Mahmood obtained B.Sc Hons in Applied Physics, MSc in Solid State Physics and PhD in Semiconductor Devices from Universiti Sains Malaysia. Her research interests are in semiconductor devices, nanostructure’s fabrication (III-Nitrides and Silicon), photonics and optoelectronic application, photodetectors, gas and environmental sensors. She is currently working as a senior lecturer at Department of Applied Sciences, Universiti Teknologi MARA, Pulau Pinang.
Nurul Syuhadah Mohd Razali obtained MSc in Electrical Engineering at UiTM Pulau Pinang. Her research interests are in the fabrication and characterization of porous structures for application in semiconductor devices.
Aslina Abu Bakar obtained PhD in Electrical Engineering from the University of Queensland in 2012. Her research interest includes Microwave Imaging, Wearable Antenna and UWB microwave imaging applications. Currently, she is a Senior Lecturer at Universiti Teknologi MARA, Pulau Pinang.