The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model
Abstract
Purpose
This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD).
Design/methodology/approach
The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm.
Findings
The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps.
Originality/value
It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.
Keywords
Acknowledgements
The authors gratefully acknowledge the support of the Universiti Kuala Lumpur British Malaysian Institute and Universiti Putra Malaysia.
Citation
Abu, M.A., Harun, H., Yazdi Harmin, M., Abdul Wahab, N.I. and Abdul Kadir, M.K. (2016), "The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model", World Journal of Engineering, Vol. 13 No. 6, pp. 540-546. https://doi.org/10.1108/WJE-09-2016-0088
Publisher
:Emerald Group Publishing Limited
Copyright © 2016, Emerald Group Publishing Limited