Microtech 2005

Citation

Ling, J. (2005), "Microtech 2005", Microelectronics International, Vol. 22 No. 2. https://doi.org/10.1108/mi.2005.21822bac.001

Microtech 2005

Keywords: Conferences, Electronic engineering

Microtech 2005

Møller Conference Centre, Cambridge, 1-2 March 2005

The Møeller Centre in Cambridge proved popular in 2004, so much so that iMaps returned again this year and plans to do so again next year. Welcoming the delegates, Steve Muckett, iMaps Chairman, also gave all of the many exhibitors a chance to introduce themselves so that people were aware of what was on display in the foyer. There was much to see.

1 March

In the conference room, the first speaker was Andy Longford runs PandA Europe UK and he spoke about the trends in Advanced Packaging Technologies. He produced a quotation “Packaging is becoming the bottleneck as the technology gap between chip and PCB widens”, which underscored the problem. Whilst iMaps members are primarily concerned with board to connector packaging, they should be aware that the forecast for semiconductor packaging materials is for 40 percent growth, with QFN (leadless packages) being the fastest growing package.

Wafer level packaging (WLP) is coming into its own where it overlaps the downward trends in leadframes. The need to get more memory in a small package will drive wafer level packaging. Also, embedded passives are coming in, and 2006 will see the use of polymer multifunctional blocks. The driver is photonics, and with MEMS disappearing, it is now all about a system in a package (SIP). Cost drivers include: form factor; time to market; sources of equivalent parts; an ability to refresh product; fabrication infrastructure; and the pressure constantly for smaller faster and cheaper. It is called progress.

Future developments will include stacked dies, 50μm thick. Out will go MCM, in will come DCA, COB, HDP (high-density package) and Andy looked at the Stacked Chip Package Roadmap. WLP challenges include bumping pitch, materials, low K passivation; QFN challenges include handling, marking, materials, and test conditions. Summarising, Andy commented that whilst most advanced packaging volume is done in the Pacific region, much innovation work is done in Europe, essential if we are to stay ahead.

The next speaker was Thomas Oppert from Pac Tech GmbH, Berlin. His company was developing a low cost European wafer bumping service. He mentioned the difficulties that were faced at the beginning, when everyone thought that electroless ni/au was a crazy idea, technically impossible, and economically unfeasible. Rather like the idea of the motorised carriage! It all began in 1985, with the first active electroless bumped wafer being produced in 1989. They now licence the technology to Japan and the USA.

The process possibilities include FC with ACF, Ultra fine pitch LCD Driver, and it is used for copper pad passivation, for wire bonding of high power devices, and for FC and wire bonding. There is also a nickel palladium gold bumping system for high temperature applications. Lot of interest at the moment from European customers. The advantages of electroless in/au include: low capital investment cost: high throughput; it is a maskless process; it has low process cost compared to electroplating; it has 300mm compatibility; proven reliability; compatibility with all FC assembly processes; is suitable for al and cu pad metallisation; and is compatible with wire bonding. The company now have six Pacline 300 systems operating in the field.

Dr Ursula Meyer looks after Europe technically for March Plasma Systems, and explained about the various applications of Plasma Treatment. So what is plasma? Plasma is highly energised ionised gas. It is used for contamination removal, and it cleans and activates the surface of a substrate. This activation makes the surface receptive for the deposition of thin films. It can also be used for etching, and for crosslinking. Other applications include die bonding, where it is used for cleaning to remove metal oxides, where it can render a surface suitable to increase adhesion, and decrease delamination. Used for wire bonding it will improve yield and reliability, maximise pull strength, and increase uniformity (CpK).

Plasma applications include advanced packaging, such as molding, where it will increase surface energy, enhance flow characteristics, reduce wire bond damage due to sweep, remove organic contamination, and improve peel strengths. Plasma may also be used for flip chip underfilling. Here you do need to understand plasma, and understand the materials, the chemistry, the plasma itself. In the underfill role there are challenges: you have to consider the die size, the bump density, the die pitch (gap) and the materials. The die size is important, as the size determines the amount of underfill required. With an increase in die size you have higher contact angle.

What does plasma do for the underfill process? It maximises the wicking speed, allows for an increase in fillet height, and makes for maximum fillet uniformity and underfill adhesion. The more uniform the fillet height the more reliable the packaged device. Not all plasma conditions will produce good results, but optimised plasma will increase fillet height, improve fillet uniformity, and optimum underfilling for best performance.

Colin Edge is from Bookham Technologies, and discussed the future packaging requirements for photonics. He looked at the current photoelectronic packaging and the future priorities, as well as ongoing developments in packaging components that generate, modify or detect light. Such components are used in the space, defence, medical, automotive, and communications industries. The optical transmitter is a highly sophisticated component, difficult to manufacture and very demanding. At present, for fibre optics, conventional packaging involves metal enclosures, with active temperature control of lasers for power, ageing and wavelength. There are microelectronic components there for active optical alignment, and the results are gold boxes, offering high performance at high cost. So the priorities now, in a mature market, are lower cost, a smaller footprint, lower power consumption, and increased functionality.

Lower cost is not just a question of using cheaper parts, or moving labour intensive stages to low wage economies; longer-term solutions are needed. Relevant here is hermetic packaging, monolithic integration, and uncooled operation. Packages have to be hermetically sealed, they have to have a10-year life cycle. LCC ceramics allow a reduction in cost, and liquid crystal polymers are being investigated. But an enclosure must provide mechanical stability for optical coupling, and here passive alignment may lend a helping hand, as semi-passive techniques can realise high coupling efficiency. But you still may have to “tweak” it.

Full monolithic integration based on inP could reduce the optical assembly to one fibrecoupling interface. Uncooled operation would be wonderful, but needs the operation of a DW/DM tunable laser. If the trends are towards an increase in functionality, then this might be possible with the use of a BGA style electrical interface, but you also need a thermal interface.

Optoelectronic packaging has remained expensive and labour intensive for the last 20 years, but the changes now required are driven by chip and packaging development. In the future the electronic chip must be designed for packaging as well as functionality. Then you can have increased levels on monolithic integration, and much might be possible.

Steve Pope also works for Bookham Technologies, and he presented a paper on reliability and endurance testing for a liquid crystal variable optical attentuator (VOA) durable box. First of all he explained how it works. The relatively new use of liquid crystal cell in telecommunication equipment has thrown up some reliability issues. Problems include polariser attack and glue seal integrity against a requirement for devices integrated into telecoms modules that must operate in hostile environments over an operating lifetime of 25 years. An extremely detailed paper showed how LC devices from CoAdna Photonics had fulfilled the requirements for a co-packaged VOA and are now available.

Tony Carter of TMS Technologies Ltd knows about thermal management systems. TMS's are major features right now. Moores Law drives semiconductor technology; semiconductors double in quantity every 1.5 years, and their power doubles every 3 years. All that power means heat, and here transistor leakage currents are a major concern. This means leakage of up to 40 percent of power, or some 60w per chip. The impact of hot spots is that they degrade reliability and performance, given that you can have a 10°C variation across a chip. Challenges include thermal resistance of all the interfaces; CPU power delivery systems (increasing current with decreasing voltage gives overall reduced efficiency), and you have to accommodate constant Form Factors.

Thermal analysis and engineering skill is to integrate activities into one uniform design, from die through to servers and data centres. Hot spots can be alleviated with excellent thermal spreading. TMS is based on the use of high thermal conductive graphite, developing a direct encapsulating technology, a graphite with four times the thermal conductivity of copper and 4 times less the density. Hence a potential to provide optimised microelectronics cooling, and manufacture devices which can be electrically conducting or electrically insulating. The specific thermal conductivity of this graphite product is 15 times better than copper, has a micron level surface flatness can be preserved over centimetres and has proven integrity in high radiation environments. It is now an ideal basic substrate for hybrids, and this new product can provide for greatly improved thermal management in microelectronics. Such is the excellence of thermal conductivity that it can be used to improve existing systems, and can provide external chip thermal management, at reasonable costs for high volume.

Dr David Jacobson possesses many talents, being a full time university professor as well as working for Sandvik Osprey Ltd. He told us about a low cost lightweight solution for RF and Microwave packaging using aluminium – silicon alloys. This product has now reached commercial maturity and lends itself admirably to RF and Microwave packaging, both of which need a leak-proof environment. In a comparison between known materials he highlighted strengths and weaknesses, and this lead neatly to reasons why CE11 came into being, an alloy of aluminium and silicon, spray formed in a special process. This alloy comes in a range of types that range across the CTE spectrum, are lightweight, have good thermal conductivity and comprise well- behaved materials. They can be readily machined with solid carbide or PCB drilling tools, with similar costs to those pertaining. Reamed out it will proffer very strong threads, is electroplateable, and the feedthrough technology is good with laser drilling and welding. CE11 (Al-50Si) costs the same as titanium, but given all the advantages that it offers (laser-lid sealing, laser welding, freedom from compressive stress) you to look at the overall costs.

2 March

Wolfgang Reinert works at the Fraunhofer Institute, and came along at very short notice to talk about process integration of patterned getter films in vacuum wafer bonding. This is a project now nearing completion, and initially driven by the automotive industry who require a low cost highly reliable MEMS packages with a 15 year guaranteed life in the temperature range from -40 to +125°C, a package with an internal mass of only 0.25mm³. Fraunhofer Institute have produced the Patterned Getter (PaGe) Wafer which came about because they wanted to develop a vacuum wafer bonding technology using eutectic bonding in combination with getter materials inside the cavities enabling a long term vacuum of 10/4mbar lasting for 10 years. The package measures 3mm× 1mm and acts as a gyroscope. Bonding takes place at 400°C. High bond strength.

The PaGeWafer uses a non- evaporable getter (NEG) material and is MEMS compatible, with no particle emission, with optimised getter morphology for increased sorption qualities. Argon outgassing had been a problem during development, so no argon-based sputtering could be used. The PaGeWafer passes 1,000 cycles from -40 to +125°C, and they have achieved 5×10mbar at the lower vacuum limit for MEMS construction over 15 years.

No surprise to learn that this paper won the iMaps Outstanding Technical Paper Award at the conference, but the modest Herr Reinsert had already left for his flight back to Germany.

Dr Jerry Sergent is the Chairman of the Electrical Engineering Department at Fairfield University in Connecticut, USA, and flew over especially to tell us about his studies of the thermally induced mechanical stresses on mounted components. Stress, he opened, occurs due to a CTE mismatch between the component and the board. So there are two areas of interest.

The first is with a chip capacitor soldered to a circuit board. Here stress begins to generate when the solder solidifies, and continues to increase as the structure cools. Jerry developed a matrix of variables using different size capacitors, from 1,206 to 2,225. Typical stress values required to break the capacitors range from 250 to 300Mpa. A series of tests, explained as 2D models, showed that the level of stress increases in line with fillet height. A 3mil fillet height showed minimal stress but he was not entirely sure why! You do need to control the solder volume, and control the pad size. The 1812 capacitor is the largest size allowable if the lowest operating temperature is -40°C.

The second area is a die on a ceramic chip carrier. Through a series of mathematical calculations Dr Sergent explained that the stress is related to bond thickness, as this gets thicker it can absorb more of the stress, bringing it down below the critical level. High tin content solders were far the best, and the worst were tin/lead. You may minimise stress on silicone die by increasing the bond thickness, and with proper handling and processing during die prep. He has yet to look at chip on board.

A paper which probably created the greatest amount of interest, if the number of questions was anything to go by.

Thomas Bartnitzek hails from VIA Electronic GmbH in Hemsdorf in Germany. He gave us the results of project into LTCC Phase shifter Modules with multiple MEMS-switch integration. This EC funded project is to produce a car roof antennae for satellite data communication. The challenge is that the car is moving, and this is truly mobile communication, using an LTCC for 3b phase shifters for 45°, 90° and 180° angles to get the signal transmitted in the frequency range of 1.6-2.0GHz. An LTCC test run showed that capacitors with typical dielectric will cause problems, with capacitance too low and request of area not acceptable, and the big area needed for a capacitor leads to loss vs. GND.

So they looked at integration of LTCC tapes with higher k, and thick film printing of high k dielectric pastes, as well as the use of very thin standard tapes. The use of high k thick film paste showed that different thicknesses were possible, and had lower thickness than tape, but showed strong warping and an impairment of neighbouring RF structures. A 30μm thick high k tape showed low warpage values, and 951 C2 tape showed no significant thickness addition, and full material compatibility. Essentially high k tape is better than high k thick film paste. During the coming weeks they will see the construction of a demonstrator, its integration into an antenna, and the full testing of a prototype.

Nihal Sinnadurai runs a company called Attac and gallantly stood in at short notice to present a paper on LTCC – an opportunity technology for RF and photonics System-In-Packages at the high end. What is a SIP? What are the requirements for SIPs? They are a module containing one or more ICs, where passive components can be added, to realise an integral functional unit. A reduced design stage, with material cost reduction and assembly costs, it is miniaturised, has improved electrical performance and has continuous product improvement built in. SIPs are needed as carriers, for high line resolution, and assembly options are many; interfaces can be electrical, optical, fluidic and thermal. Low temperature co-fired ceramics (LTCC) can be used for Sips, you can embed passives, it is thick film compatible, with many good properties and advantages, and you can embed thin films. Capacitors in LTCC are required for microwave applications, for coupling, for decoupling, for a RF bias network. These latches can be used for a range of applications, with higher resonant frequencies, but lower quality factors; the integration capability however, is an important benefit of printed capacitors, it allows for the standardisation of components for designers.

Dr Kevin Gallop from technology for industry talked about developments in cost effective packaging technology for microsystems devices. In his overview, he looked at examples, such as inertial sensors, typically used in airbag accelerometers, where a sense of motion of a physical object could be measured by the use of sensitive mechanical elements on a silicon chip. The input – the motion of the encapsulated chip, the output an electrical signal. With a Side airbag sensor there are fluidic sensors, so the input is static or flowing fluid, and the output is again an electrical signal. There are fibre optic devices, where the input is optical and electrical signals, and the output once again optical and electrical signals.

Challenges abound. Microsystem packaging comes in all sizes and shapes, is non-standard, has low volumes, is sensitive to packaging materials, and environment during packaging and inside the package. Also, there is a lack of trained personnel.

New solutions offer themselves in the shape of WLPs, which protect devices during standard assembly procedures. They are as follows:

1. 1.

   Wafer bonding. Bonds MEMs wafer to wafer with manufactured cavities using standard processing. Benefits – uses standard MEMS processing steps, well characterised, high yielding, and stackable.

2. 2.

   Flip chip assembly – use flip chip technique to place individual lids.

3. 3.

   Benefits – flexibility, but a query on speed and cost.

4. 4.

   Deposited caps described. Benefits – batch processing, high packing density; pot. Low cost, hermetic, complex feedthrough OK.

5. 5.

   Subsystem integration.

6. 6.

   Optical microsystems.

7. 7.

   Microfluidics – ink-jet print heads.

Emerging trends. Packaging is one of the most important barriers to the commercialisation of microsystems and the most significant cost element in the finished product. Packages will become increasingly functional as more sophisticated designs emerge and polymer microsystems become more widespread.

Martin Schoeppler is the VP Strategic Business Development for Spectra, Inc., based in Santa Clara, California, who also took the trouble to fly over for Microtech 2005. Spectra make ink-jets, and they make them using MEMS processing, He said that they build everything in-house, having been unable to locate a secure supply externally. They produce silicon MEMS with piezoelectric ceramic layer which is key to on-demand pumping for ink-jet. They make a silicon wafer, then PZT material applied, then a descender etch to create an orifice, in fact to create a complete inkjet head via the MEMS process. This is good when you want to model and scale, and make prototype ink-jet heads. This is cost effective for small runs, and is timely.

Spectra believe that ink-jet will play a major part in microelectronic packaging. Ink-jet is essentially non- contact printing, and follows the substrates contours and roughness. It is an easy to use system, and should have high drop placement precision. Smaller drops means image quality, needed for IC interconnects, PCB tracks, transistors and backplanes. Higher frequencies will improve productivity through a multi-pulsing system. Ink-jet enables new additive material deposition, and it is known that flexible substrates require new materials and deposition technology. Spectra have proved that MEMS- based ink-jet is compatible with complex fluids, that silicon technology is scalable, and that printed electronics will become a reality.

Another excellent Microtech conference, professionally constructed, managed and orchestrated, with a totally complimentary exhibition in accompaniment.

Microtech 2006 will be at the Møeller Centre on 7 and 8 March next year.

The theme will be. System in Package.

The title will be Design, Manufacture and Test for System in Package Technologies.

The message is don't miss it.

John LingAssociate Editor, Microelectronics International