Effects of High Electrical Stress in PCBs

Abstract

The increasing level of integration in PCB technology demands from the designer a new level of sensitivity to high electrical field problems and to the degradation processes that may be involved. High electrical fields interacting with thermal and mechanical stresses could lead to the growth of ‘latent defects’, not easily identifiable during final stage acceptance tests, that could lead the PCB's failure during service. The paper discusses degradation mechanisms which can lead to dielectric failure, together with first results relevant to a wider research project regarding identification of latent defects in PCBs and the development of new test procedures.

Citation

Travi, C., Albertini*, M. and Gemme*, C. (1996), "Effects of High Electrical Stress in PCBs", Circuit World, Vol. 22 No. 2, pp. 16-18. https://doi.org/10.1108/03056129610799930