VLSI Packaging

Abstract

The ever greater complexity of VLSI devices is resulting in increases in pin count, power dissipation, and chip area. Furthermore, the increase in speed because of the smaller feature sizes leads to more stringent electrical requirements on the packaging. For high reliability under adverse ambient conditions, hermetic sealing is mandatory. However, for less severe requirements, plastic encapsulation is proving a cost‐effective alternative. It is expected that improvements in plastic materials and in chip surface passivation will further enhance the reliability of plastic‐packaged VLSI devices. Packaging materials and processes, as well as packaged shapes, will have to be modified to cope with the demands of future VLSI devices.

Citation

Reiner, H. (1985), "VLSI Packaging", Microelectronics International, Vol. 2 No. 2, pp. 9-13. https://doi.org/10.1108/eb044169