Printed Wiring Board Inner Layer Contamination Study

Abstract

Electrical leakage beyond control levels did not occur in high temperature and humidity stressing of surface insulation resistance patterns when the relatively high contamination levels of 5 and 10 µg LiBr/cm were laminated into a simple test multilayer board structure. When sputtered layers of LiF, LiBr and NaCl were covered by a thin 0·002 in. lamination layer, generally similar results were obtained at 35°C/90% relative humidity and even at 85°C/85% relative humidity. Biasing of some samples at 85°C/85% relative humidity out to 400 hours did cause leakages which vary from one to three decades above the controls, but drifting with time beyond 96 hours towards a shorting condition, or to the level of unlaminated samples, on a leakage per square basis was not observed. Because the surface insulation resistance per square concept did not hold in these experiments, the surface leakage mechanism is apparently overridden by bulk leakages which occur in parallel in the laminations.

Citation

Chan, A.S.L., Shankoff, T.A. and Culver, D. (1990), "Printed Wiring Board Inner Layer Contamination Study", Circuit World, Vol. 17 No. 1, pp. 10-14. https://doi.org/10.1108/eb046107